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Application Note 9846
be lower, and their maximums should rarely all occur
simultaneously. Output tolerances and current ratings (with
the exception of the 2.5/3.3V MEM output current rating in
sleep state) can be adjusted by properly selecting the
components external to the HIP6501A.
TABLE 1. HIP6501AEVAL1 MAXIMUM OUTPUT LOADING
5VSB
5V DUAL
3.3V DUAL
ACTIVE STATES
SLEEP STATES
TOL.
OUTPUT
VOLTAGE
2.5/3.3V MEM
3.3V DUAL
5V DUAL
I OUT
4A
3A
2.5A
dI OUT /dt
1A/ μ s
0.2A/ μ s
0.1A/ μ s
I OUT
250mA
600mA
200mA
dI OUT /dt
1A/ μ s
0.2A/ μ s
0.1A/ μ s
(static/
dynamic)
5% / 9%
9% / 9%
9% / 9%
123 4 >
2.5V MEM
T0 T1
T2
The maximum current draw on the 2.5V MEM output systems
employing RDRAM memory) can be as high as 7-8A for
Ch1 1.00V BW
Ch3 1.00V BW
Ch2 1.00V BW
Ch4 1.00V BW
5.00ms Ch4
2.98V
short periods of time during memory initialization. To avoid
having to design a high-current output which would be used
at its fullest potential only during a very short period of time,
we recommend reducing the memory clock speed during
initialization. This method should result in a significant
reduction in the current needed during initialization. This
current can then be delivered through a single external pass
transistor connected directly to the DRV2 pin.
HIP6501AEVAL1 Performance
Figures 2-6 depict the evaluation board’s performance
during a few typical operational situations. To simulate
minimum loading conditions, unless otherwise specified, the
outputs were loaded with 65 ? resistive loads.
Sleep-State Start-Up
Figure 2 shows a typical start-up into S3 sleep state while all
outputs are enabled (EN3VDL = 0, EN5VDL = 1). As 5VSB
is applied to the board, SW1 and SW3 are off, while SW2 is
on. At time T0 the input supply exceeds the power-on-reset
(POR) threshold. Three milliseconds afterwards, at time T1,
the soft-start clamp is removed and the outputs start to ramp
up toward their target value, which they reach at time T2.
The 5V DUAL output has a slightly different ramp-up due to
the fact that it undergoes a different soft-start than the
remainder of the output voltages. The 5V DUAL output is not
actively regulated, as is the case with the 2.5V MEM and
3.3V DUAL outputs in S3, but rather switched on through a
P-MOS or PNP switch. An error amplifier is thus provided for
the 5V DUAL output just for the purpose of providing a
smooth, controlled output voltage rise. This error amplifier
uses a different, soft-start derived, control signal to achieve
FIGURE 2. HIP6501AEVAL1 START-UP IN SLEEP STATE (S3)
WITH ALL OUTPUTS ENABLED
Active-State Start-Up
Figure 3 also shows a start-up sequence, but this time into
active state (S0,S1). As the enable pins only configure the
sleep state voltage support, this start-up sequence will be
the same, regardless of EN3VDL and EN5VDL status. In
Figure 3, SW1, SW2 and SW3 are all off and 5VSB is
applied to the board. Active state operation is enabled by
switching on SW1, just 3-4ms before T0. At time T0, the 12V
input exceeds the under-voltage threshold and the internal
50ms (typical) timer is initiated. Between T0 and T1, the
3.3V DUAL and 5V DUAL outputs undergo a quasi soft-start,
due to conduction through the body diodes of the active
N-MOS switches (Q3A and Q3B). At time T1 the timer
expires and the two N-MOS transistors are turned on;
simultaneously the 2.5V MEM output begins a soft-start cycle,
being charged up through the external pass transistor,
Q1.1B. The ramp-up of the 2.5V MEM output ends at T2,
when it reaches its regulation limit.
12VIN
5V DUAL
3.3V DUAL
the controlled ramp-up of the output.
4 123 >
2.5V MEM
T0
T1
T2
Ch1 1.00V BW
Ch3 1.00V BW
Ch2 1.00V BW
Ch4 2.00V BW
10.00ms Ch4
7.96V
FIGURE 3. HIP6501AEVAL1 START-UP IN ACTIVE STATE
(S0,S1) WITH ALL OUTPUTS ENABLED
3
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